11
I
F
PULSE GEN.
= 50 Ω
R
*
56 Ω
CC
B
A
D.U.T.
Z
+5 V
O
t , t = 50 ns
R
*
r
f
56 Ω
V
CC
CC
D.U.T.
f = 100 Hz
= 0.5ms
R
L
1.0 µF
I
+5 V
F
t
PULSE
V
CC
V
O
R
1.0 µF
L
V
O
I
MONITOR
F
V
FF
GND
Rm
C **
L
V
CM
GND
+
–
PULSE GEN.
* SEE NOTE 11
** C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
* SEE NOTE 11
L
Figure 9. Test Circuit for Transient Immunity and
Typical Waveforms.
Figure 8. Switching Test Circuit (f, tP
not JEDEC registered).
V
CC
R
1
I
LEAK
R
2
D.U.T.
V
CC
2.4 - V
F
>
<
R
R
2
I
F
V
O
V
- V - I
R
2
CC
F
F
1
I
+ I
F
LEAK
GND
R
MAY BE OMITTED
2
IF ADDITIONAL FANOUT
IS NOT USED.
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.
HP [ HEWLETT-PACKARD ]
