3
Functional Diagrams
16 pin DIP
Through Hole
4 Channels
1
8 pin DIP
Through Hole
1 Channel
V
CC
8
8 pin DIP
Through Hole
2 Channels
1
V
CC
V
O1
V
O2
8
16 pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
15
V
CC2
1
16
2
1
16
19
20
V
O2
GND
2
V
O1
GND
1
V
CC1
13
12
7
V
OUT
6
5
2
3
4
V
CC
V
O1
V
O2
V
O3
V
O4
GND
15
3
2
3
4
7
6
5
2
3
4
V
CC
V
O1
V
O2
V
O3
V
O4
GND
15
2
14
13
10
14
4
3
13
GND
GND
7
12
8
5
12
5
6
7
8
11
10
9
6
7
8
11
10
9
Note: All DIP and flat pack devices have common V
CC
and ground. LCCC (leadless ceramic chip carrier) package has isolated channels
with separate V
CC
and ground connections.
Outline Drawings
16 Pin DIP Through Hole, 4 Channels
20.06 (0.790)
20.83 (0.820)
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
8.13 (0.320)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Leaded Device Marking
Agilent DESIGNATOR
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Agilent CAGE CODE*
Leadless Device Marking
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
•
•
*QUALIFIED PARTS ONLY
*QUALIFIED PARTS ONLY