Propagation Delay, Pulse Width
Distortion and Propagation Delay Skew the difference between tPHL and
Propagation Delay is a figure of
merit, which describes how
quickly a logic signal propagates
Pulse Width Distortion, PWD, is
If the parallel data is being sent
through channels of the digital
isolators, differences in propaga-
tion delays will cause the data to
arrive at the outputs of the
digital isolators at different
times. If this difference in
tPLH and often determines the
maximum data rate capability of
a transmission system. PWD can
through a system as illustrated in be expressed in percent by
Figure 3.
dividing the PWD (in ns) by the
minimum pulse width (in ns)
propagation delay is large
The propagation delay from low to being transmitted. Typically, PWD enough, it will limit the maxi-
high, tPLH, is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low, tPHL, is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low.
on the order of 20–30% of the
minimum pulse width is tolerable. parallel data can be sent through
the digital isolators.
mum transmission rate at which
Propagation Delay Skew, tPSK
,
and Channel-to-Channel Skew,
tCSK, are critical parameters to
consider in parallel data trans-
mission applications where
synchronization of signals on
parallel data lines is a concern.
tPSK is defined as the difference
between the minimum and
maximum propagation delays,
either tPLH or tPHL, among two or
more devices which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and operat-
ing temperature). tCSK is defined
as the difference between the
minimum and maximum propaga-
5 V CMOS
INPUT
tion delays, either tPLH or tPHL
,
50%
V
IN
among two or more channels
within a single device (applicable
to dual and quad channel de-
vices) which are operating under
the same conditions.
0 V
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
OUT
10%
10%
V
OL
As illustrated in Figure 4, if the
inputs of two or more devices are
switched either ON or OFF at the
same time, tPSK is the difference
between the minimum propaga-
tion delay, either tPLH or tPHL, and
the maximum propagation delay,
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL
.
VIN
DATA
50%
INPUTS
either tPLH or tPHL
.
CLOCK
2.5 V
CMOS
VOUT
As mentioned earlier, tPSK, can
determine the maximum parallel
data transmission rate. Figure 5
shows the timing diagram of a
typical parallel data transmission
application with both the clock
and data lines being sent through
the digital isolators. The figure
shows data and clock signals at
the inputs and outputs of the
digital isolators. In this case, the
data is clocked off the rising edge
of the clock.
tPSK
DATA
50%
OUTPUTS
CLOCK
VIN
tPSK
tPSK
2.5 V
CMOS
VOUT
Figure 5. Parallel Data Transmission.
Figure 4. Timing Diagrams to Illustrate
Propagation Delay Skew.
11
HP [ HEWLETT-PACKARD ]
