7
Typical Characteristics All typical values are at TA = 25°C, VCC = 5 V, unless otherwise specified.
Parameter
Hysteresis
Symbol
Typ. Units
Conditions
IHYS = ITH+ - ITH-
Fig.
Note
IHYS
1.2
1.1
mA
V
1
VHYS
VILC
VHYS = VTH+ - VTH-
Input Clamp Voltage
-0.76
V
VILC = V2 - V3; V3 = GND;
IIN = -10 mA
Bridge Diode
VD1,2
0.62
IIN = 3 mA (see schematic)
Forward Voltage
VD3,4
RI-O
0.73
1012
Input-Output Resistance
Input-Output Capacitance
Input Capacitance
Ω
VI-O = 500 Vdc
9
CI-O
CIN
2.0
50
pF
pF
f = 1 MHz, VI-O = 0 Vdc
f = 1 MHz; VIN = 0 V,
Pins 2 & 3, Pins 1 & 4 Open
Output Rise Time
(10-90%)
tr
tf
10
µs
µs
7
7
Output Fall Time
(90-10%)
0.5
Notes:
voltage, V , to ensure that the output
CM
7. Logic low output level at Pin 6 occurs
under the conditions of V ≥ V as
1. Maximum operating frequency is
defined when output waveform (Pin 6)
attains only 90% of V with R = 1.8
kΩ, C = 15 pF using a 5 V square
wave input signal.
2. Measured at a point 1.6 mm below
seating plane.
3. Current into/out of any single lead.
4. Surge input current duration is 3 ms at
120 Hz pulse repetition rate. Transient
input current duration is 10 µs at
120 Hz pulse repetition rate. Note that
will remain in a Logic High state (i.e.,
IN
TH+
V
> 2.0 V). Common mode transient
well as the range of V > V – once
O
IN
TH+
TH
CC
L
immunity in Logic Low level is the
maximum tolerable dVCM/dt of the
V
has exceeded V
. Logic high
IN
L
output level at Pin 6 occurs under the
conditions of V ≤ V
as well as the
common mode voltage, V , to ensure
IN
TH-
CM
range of V < V
decreased below V
once V has
IN
that the output will remain in a Logic
IN
TH+
.
Low state (i.e., V < 0.8 V). See
TH-
O
8. The ac voltage is instantaneous
voltage.
Figure 8.
14. In applications where dV
may
CM/dt
9. Device considered a two terminal
device: Pins 1, 2, 3, 4 connected
together, Pins 5, 6, 7 8 connected
together.
10. This is a momentary withstand test,
not an operating condition.
exceed 50,000 V/µs (such as static
discharge), a series resistor, R
,
CC
should be included to protect the
detector IC from destructively high
surge currents. The recommended
maximum input power, P , must be
observed.
IN
5. Derate linearly above 100°C free-air
temperature at a rate of 4.26 mW/°C.
Maximum input power dissipation of
195 mW allows an input IC junction
temperature of 150°C at an ambient
value for R is 240 Ω per volt of
CC
11. The t
propagation delay is
allowable drop in V (between Pin 8
CC
PHL
measured from the 2.5 V level of the
leading edge of a 5.0 V input pulse (1
µs rise time) to the 1.5 V level on the
leading edge of the output pulse (see
Figure 7).
and V ) with a minimum value of
CC
240 Ω.
15. D and D are Schottky diodes; D
temperature of T = 125°C with a
1
2
3
A
and D are zener diodes.
typical thermal resistance from
4
16. Standard parts receive 100% testing at
25°C (Subgroups 1 and 9). SMD,
Class H and Class K parts receive
100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10 ,3 and
11, respectively.)
17. Parameters shall be tested as part of
device initial characterization and after
process changes. Parameters shall be
guaranteed to the limits specified for
all lots not specifically tested.
junction to ambient of θ i = 235°C/W.
JA
12. The t
propagation delay is
The typical thermal resistance from
PLH
measured from the 2.5 V level of the
trailing edge of a 5.0 V input pulse (1
µs fall time) to the 1.5 V level on the
trailing edge of the output pulse (see
Figure 7).
junction to case is equal to 170°C/W.
Excessive P and T may result in
IN
J
device degradation.
6. The 1.8 kΩ load represents 1 TTL unit
load of 1.6 mA and the 4.7 kΩ pull-up
resistor.
13. Common mode transient immunity in
Logic High level is the maximum
tolerable dV
of the common mode
CM/dt
HP [ HEWLETT-PACKARD ]
