Performance Characteristics
Acquisition: Analog Channels
Max Sample Rate
54621A/D, 54622A/D, 54624A: 200 MSa/s
54641A/D, 54642A/D: 2 GSa/sec interleaved, 1 GSa/sec each channel
Max Memory Depth
54621A/D, 54622A/D, 54624A: 4 MB interleaved, 2 MB each channel
54641A/D, 54642A/D: 8 MB interleaved, 4 MB each channel
Vertical Resolution
Peak Detection
8 bits
54621A/D, 54622A/D, 54624A: 5 ns
54641A/D, 54642A/D: 1 ns @ max sample rate
Averaging
Selectable from 2, 4, 8, 16, 32, 64 … to 16383
High Resolution Mode
54621A/D, 54622A/D, 54624A: 12 bits of resolution when ≥500 µs/div, (average mode with ave = 1)
54641A/D, 54642A/D: 12 bits of resolution when ≥100 µs/div, (average mode with ave = 1)
Filter
Sinx/x interpolation (single shot BW = sample rate/4 or bandwidth of scope, whichever is less) with vectors on.
Acquisition: Digital Channels (54621D, 54622D, 54641D, and 54642D only)
Max Sample Rate
Max Memory Depth
Vertical Resolution
54621D, 54622D: 400 MSa/s interleaved, 200 MSa/s each channel
54641D, 54642D: 1 GSa/s
54621D, 54622D: 8 Mb interleaved, 4 Mb ea. channel
54641D, 54642D: 4 Mb
1 bit
5 ns
Glitch Detection
(min pulse width)
Vertical System: Analog Channels
Analog Channels
54621A/D, 54622A/D, 54641A/D, 54642A/D: Ch 1 and 2 simultaneous acquisition
54624A: Ch 1, 2, 3 and 4 simultaneous acquisition
Bandwidth (-3dB)*
ac Coupled
54621A/D: dc to 60 MHz
54622A/D, 54624A: dc to 100 MHz
54641A/D: dc to 350 MHz
54642A/D: dc to 500 MHz
54621A/D: 3.5 Hz to 60 MHz
54622A/D: 54624A: 3.5 Hz to 100 MHz
54641A/D: 3.5 Hz to 350 MHz
54642A/D: 3.5 Hz to 500 MHz
Calculated Risetime
(=0.35/bandwidth)
54621A/D: ~5.8 ns
54622A/D, 54624A: ~3.5 ns
54641A/D: ~1.0 ns
54642A/D: ~700 ps
Single Shot Bandwidth
54621A/D, 54622A/D, 54624A: 50 MHz
54641A/D: 350 MHz maximum
54642A/D: 500 MHz maximum
*
Denotes Warranted Specifications, all others are typical. Specifications are valid after a 30-minute warm-up period and ± 10 ꢀC from firmware calibration temperature.
13
HP [ HEWLETT-PACKARD ]
