RFM31B
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
First Bit
Last Bit
SDO
D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 3. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An example burst write
transaction is illustrated in Figure 4 and a burst read in Figure 5. As long as nSEL is held low, input data will be
latched into the RFM31B every eight SCLK cycles.
First Bit
Last Bit
RW
=1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X =X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
nSEL
Figure 4. SPI Timing—Burst Write Mode
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
First Bit
SDO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 5. SPI Timing—Burst Read Mode
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