RFM23
Register 1Fh. Clock Recovery Gearshift Override
Bit
D7
Reserved
R/W
D6
rxready
R/W
D5
D4
D3
D2
D1
D0
crfast[2:0]
R/W
crslow[2:0]
R/W
Name
Type
Reset value = 00000011
Bit
Name
Function
Reserved
Reserved.
Improves Receiver Noise Immunity when in Direct Mode.
7
It is recommended to set this bit after preamble is detected. When in FIFO
mode this bit should be set to ―0‖ since noise immunity is controlled
automatically.
rxready
6
crfast[2:0]
crslow[2:0]
5:3
2:0
Clock Recovery Fast Gearshift Value.
Clock Recovery Slow Gearshift Value.
The gear-shift register controls BCR loop gain. Before the preamble is detected, BCR loop gain is as follows:
crgain
BCRLoopGain =
crfast
2
Once the preamble is detected, internal state machine automatically shift BCR loop gain to the following:
crgain
2crslow
BCRLoopGain =
crfast = 3‘b000 and crslow = 3‘b101 are recommended for most applications. The value of ―crslow‖ should be
greater than ―crfast‖.
97
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