RFM23
8. Auxiliary Functions
8.1. Smart Reset
The RFM23 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable
reset signal in any circumstances. Reset will be initiated if any of the following conditions occur:
Initial power on, when VDD starts from 0V: reset is active till VDD reaches VRR (see table);
When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR again;
A software reset via ―Register 08h. Operating Mode and Function Control 2,‖ : reset is active for time
TSWRST
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
Figure 23. POR Glitch Parameters
Table 22. POR Parameters
Parameter
Symbol
VRR
Comment
Min
0.85
0.03
0.7
Typ
Max Units
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
1.3
1.75
300
1.3
V
V/ms
V
SVDD
VLD
tested VDD slope region
VLD<VRR is guaranteed
1
Software Reset Pulse
Threshold Voltage
Reference Slope
TSWRST
VTSD
k
50
470
us
0.4
0.2
V
V/ms
Also occurs after SDN, and
initial power on
VDD Glitch Reset Pulse
TP
5
15
40
ms
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
51
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