RFM22B/23B
10. Register Table and Descriptions
Table 18. Register Descriptions
Add R/W
Function/Desc
Data
D4
POR
Default
D7
0
D6
0
D5
0
D3
dt[3]
D2
dt[2]
D1
dt[1]
D0
dt[0]
00
01
02
03
04
05
06
07
08
09
R
R
Device Type
Device Version
Device Status
dt[4]
vc[4]
00111
06h
—
0
0
0
vc[3]
vc[2]
vc[1]
vc[0]
R
ffovfl
ffunfl
rxffem
itxffaem
ipreainval
entxffaem
enpreainval
enwt
headerr
irxffafull
irssi
reserved
iext
reserved
ipksent
ilbd
cps[1]
ipkvalid
ichiprdy
enpkvalid
enchiprdy
pllon
cps[0]
icrcerror
ipor
R
Interrupt Status 1
Interrupt Status 2
Interrupt Enable 1
Interrupt Enable 2
ifferr
itxffafull
ipreaval
entxffafull
enpreaval
enlbd
—
R
iswdet
enfferr
enswdet
swres
antdiv[2]
xtalshft
iwut
—
R/W
R/W
enrxffafull
enrssi
x32ksel
rxmpk
xlc[4]
enext
enwut
txon
enpksent
enlbd
rxon
encrcerror
enpor
xton
00h
03h
01h
00h
7Fh
R/W Operating & Function Control 1
R/W Operating & Function Control 2
antdiv[1]
xlc[6]
antdiv[0]
xlc[5]
autotx
xlc[3]
enldm
xlc[2]
ffclrrx
ffclrtx
xlc[0]
R/W
Crystal Oscillator Load
Capacitance
xlc[1]
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R/W
Microcontroller Output Clock
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
I/O Port Configuration
ADC Configuration
Reserved
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
Reserved
Reserved
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
extitst[2]
clkt[1]
pup0
clkt[0]
gpio0[4]
gpio1[4]
gpio2[4]
extitst[0]
adcsel[0]
enlfc
gpio0[3]
gpio1[3]
gpio2[3]
itsdo
mclk[2]
gpio0[2]
gpio1[2]
gpio2[2]
dio2
mclk[1]
gpio0[1]
gpio1[1]
gpio2[1]
dio1
mclk[0]
gpio0[0]
gpio1[0]
gpio2[0]
dio0
06h
00h
00h
00h
00h
00h
pup1
pup2
extitst[1]
adcsel[1]
adcstart/adc-
adcsel[2]
adcref[1]
adcref[0]
adcgain[1]
adcgain[0]
done
10
11
R/W
R
ADC Sensor Amplifier Offset
ADC Value
Reserved
adc[7]
Reserved
adc[6]
Reserved
adc[5]
Reserved
adc[4]
adcoffs[3]
adc[3]
adcoffs[2]
adc[2]
adcoffs[1]
adc[1]
adcoffs[0]
adc[0]
00h
—
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
R/W
R/W
R/W
R/W
R/W
R
Temperature Sensor Control
Temperature Value Offset
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Wake-Up Timer Value 1
Wake-Up Timer Value 2
tsrange[1]
tvoffs[7]
Reserved
wtm[15]
wtm[7]
tsrange[0]
tvoffs[6]
Reserved
wtm[14]
wtm[6]
wtv[14]
wtv[6]
entsoffs
tvoffs[5]
Reserved
wtm[13]
wtm[5]
entstrim
tvoffs[4]
wtr[4]
tstrim[3]
tvoffs[3]
wtr[3]
tstrim[2]
tvoffs[2]
wtr[2]
tstrim[1]
tvoffs[1]
wtr[1]
tstrim[0]
tvoffs[0]
wtr[0]
20h
00h
03h
00h
01h
—
wtm[12]
wtm[4]
wtv[12]
wtv[4]
wtm[11]
wtm[3]
wtv[11]
wtv[3]
wtm[10]
wtm[2]
wtv[10]
wtv[2]
wtm[9]
wtm[1]
wtv[9]
wtm[8]
wtm[0]
wtv[8]
wtv[15]
wtv[7]
wtv[13]
wtv[5]
R
wtv[1]
wtv[0]
—
R/W Low-Duty Cycle Mode Duration
R/W Low Battery Detector Threshold
ldc[7]
ldc[6]
ldc[5]
ldc[4]
ldc[3]
ldc[2]
ldc[1]
ldc[0]
00h
14h
—
Reserved
0
Reserved
0
Reserved
0
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
R
Battery Voltage Level
IF Filter Bandwidth
vbat[4]
ndec[0]
vbat[3]
filset[3]
vbat[2]
filset[2]
vbat[1]
filset[1]
matap
vbat[0]
filset[0]
ph0size
anwait[0]
crslow[0]
R/W
dwn3_bypass
afcbd
ndec[2]
enafc
ndec[1]
afcgearh[2]
shwait[2]
crfast[2]
01h
40h
0Ah
03h
R/W AFC Loop Gearshift Override
afcgearh[1] afcgearh[0] 1p5 bypass
R/W
R/W
AFC Timing Control
swait_timer[1] swait_timer[0]
shwait[1]
crfast[1]
shwait[0]
crfast[0]
anwait[2]
crslow[2]
anwait[1]
crslow[1]
Clock Recovery Gearshift
Override
Reserved
Reserved
20
R/W Clock Recovery Oversampling
Ratio
rxosr[7]
rxosr[6]
rxosr[5]
rxosr[4]
rxosr[3]
rxosr[2]
rxosr[1]
rxosr[0]
64h
21
22
23
24
R/W
R/W
R/W
R/W
Clock Recovery Offset 2
Clock Recovery Offset 1
Clock Recovery Offset 0
rxosr[10]
ncoff[15]
ncoff[7]
rxosr[9]
ncoff[14]
ncoff[6]
rxosr[8]
ncoff[13]
ncoff[5]
stallctrl
ncoff[12]
ncoff[4]
ncoff[19]
ncoff[11]
ncoff[3]
ncoff[18]
ncoff[10]
ncoff[2]
ncoff[17]
ncoff[9]
ncoff[1]
crgain[9]
ncoff[16]
ncoff[8]
ncoff[0]
crgain[8]
01h
47h
AEh
02h
Clock Recovery Timing Loop
Gain 1
Reserved
Reserved
Reserved
rxncocomp
crgain2x
crgain[10]
25
26
27
R/W
R
Clock Recovery Timing Loop
Gain 0
crgain[7]
rssi[7]
crgain[6]
rssi[6]
crgain[5]
rssi[5]
crgain[4]
rssi[4]
crgain[3]
rssi[3]
crgain[2]
rssi[2]
crgain[1]
rssi[1]
crgain[0]
rssi[0]
8Fh
—
Received Signal Strength Indi-
cator
R/W
RSSI Threshold for Clear
Channel Indicator
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
1Eh
28
29
2A
2B
2C
2D
2E
2F
30
R
Antenna Diversity Register 1
Antenna Diversity Register 2
AFC Limiter
adrssi1[7]
adrssib[7]
Afclim[7]
adrssia[6]
adrssib[6]
Afclim[6]
adrssia[5]
adrssib[5]
Afclim[5]
afc_corr[7]
ookfrzen
ookcnt[5]
attack[1]
Reserved
crcdonly
adrssia[4]
adrssib[4]
Afclim[4]
adrssia[3]
adrssib[3]
Afclim[3]
adrssia[2]
adrssib[2]
Afclim[2]
adrssia[1]
adrssib[1]
Afclim[1]
adrssia[0]
adrssib[0]
Afclim[0]
afc_corr[2]
ookcnt[8]
ookcnt[0]
decay[0]
—
—
R
R/W
R
00h
00h
18h
BCh
26h
AFC Correction Read
OOK Counter Value 1
OOK Counter Value 2
Slicer Peak Hold
afc_corr[9]
afc_corr[9]
ookcnt[7]
Reserved
afc_corr[8]
afc_corr[9]
ookcnt[6]
attack[2]
afc_corr[6]
peakdeten
ookcnt[4]
attack[0]
afc_corr[5] afc_corr[4] afc_corr[3]
R/W
R/W
R/W
madeten
ookcnt[3]
decay[3]
ookcnt[10]
ookcnt[2]
decay[2]
ookcnt[9]
ookcnt[1]
decay[1]
R/W
Data Access Control
enpacrx
lsbfrst
skip2ph
enpactx
encrc
crc[1]
crc[0]
8Dh
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