RFM22
Register 03h. Interrupt/Status 1
Bit
D7
ifferr
R
D6
itxffafull
R
D5
ixtffaem
R
D4
irxffafull
R
D3
iext
R
D2
ipksent
R
D1
ipkvalid
R
D0
icrerror
R
Name
Type
Reset value = xxxxxxxx
Bit
Name
Function
FIFO Underflow/Overflow Error.
7
ifferr
When set to 1 the TX or RX FIFO has overflowed or underflowed.
TX FIFO Almost Full.
itxffafull
6
When set to 1 the TX FIFO has met its almost full threshold and needs to be
transmitted.
TX FIFO Almost Empty.
ixtffaem
irxffafull
5
4
When set to 1 the TX FIFO is almost empty and needs to be filled.
RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full
threshold and needs to be read by the microcontroller.
External Interrupt.
When set to 1 an interrupt occurred on one of the GPIO‘s if it is programmed
so. The status can be checked in register 0Eh. See GPIOx Configuration
section for the details.
iext
3
Packet Sent Interrupt.
ipksent
ipkvalid
icrerror
2
1
0
When set to1 a valid packet has been transmitted.
Valid Packet Received.When set to 1 a valid packet has been received.
CRC Error.
When set to 1 the cyclic redundancy check is failed.
When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting
the nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the
enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled
in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and
will not be cleared by reading the register.
75
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