RFM22
The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in
―Register 1Dh. AFC Loop Gearshift Override,‖), the Frequency Offset shows the results of the AFC algorithm for the
current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC. In
general two bytes of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened
by about 8 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver
and to detect the preamble (see "6.7. Preamble Length"). The AFC corrects the detected frequency offset by
changing the frequency of the Fractional-N PLL. When the preamble is detected, the AFC will freeze. In multi-packet
mode the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. An
automatic reset circuit prevents excessive drift by resetting the AF Cloop when the tuning exceeds 2 times the
frequency deviation (as set by fd[8:0] in register 71h and 72h) in high band or 1 times the frequency deviation in low
band. This range can be halved by the ―afcbd‖ bit in register 1Dh. If needed, fd[8:0] can have a different value in RX
mode compared to TX mode.
In TX mode, the "Register 73h. Frequency Offset 1" is used to provide an offset to the programmed transmit
frequency. This offset allows fine tuning of the transmit frequency to account for the variability of the TX reference
frequency. Note that reading this register shows the frequency offset calculated from the last AFC action, not what
was previously written to the Frequency Offset register.
The amount of feedback to the Fractional-N PLL before the preamble is detected is controlled from afcgearh[2:0].
The default value 000 relates to a feedback of 100% from the measured frequency error and is advised for most
applications. Every bit added will half the feedback but will require a longer preamble to settle. The amount of
feedback after the preamble is detected is controlled from afcgearl[2:0].
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit
times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed
to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of
the AFC cycle before the preamble is detected can be programmed with shwait[2:0] (―Register 1Eh. AFC Timing
Control,‖). It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and
2 for settling). The duration of the AFC cycle after the preamble detection and before the end of the preamble can be
programmed with lgwait[2:0]. It is advised to use the default value 000 such that the AFC is disabled after the
preamble is detected.
Frequency Correction
RX
TX
AFC disabled
AFC enabled
Freq Offset Register
Freq Offset Register
AFC
Freq Offset Register
POR
Def.
Function/Descrip
tion
D7
D6
D5
D4
D3
D2
D1
D0
Add R/W
afcbd enafc
afcgearh afcgear afcgear
[2] h[1] h[0]
AFC Loop Gearshift
Override
R/W
afcgearl[2] afcgearl[1] afcgearl[0]
40h
1D
27
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