RFM22
6.Implement normal operation.
Resolution: Will be fixed in the next revision.
7. Description: When tuned to a channel that is a multiple of 30 MHz sensitivity is degraded.
Impacts: Sensitivity will not meet specified value.
Workaround: Avoid using channels that are a multiple of 30 MHz. Contact Silicon Labs‘ customer support for
instructions on shifting the XTAL frequency if a specific frequency is required.
Resolution: Will be fixed in the future revision.
8. Description: In FSK/GFSK TX mode the preamble length is one bit less than the programmed value.
Impacts: Preamble length will be one bit less than expected if the packet handler is used in TX mode. For
example, if a 32-bit preamble is selected to be added to the data payload only 31 bits will be added.
Workaround: Add an extra nibble of preamble to the preamble length register or do not use the automatic
packet handler in TX mode.
Resolution: Will be fixed in the next revision.
9. Description: Register modifications needed for correct operation.
Impacts: PLL, RX and TX current consumption.
Workaround: Change Registers 59 = 00, 5A = 03h, and 66 = 02h.
Resolution: Default values will be updated in the next revision.
10. Description: Device operation below –25 °C.
Impacts: Frequency tuning.
Workaround: Set register 65h to A1h prior to the PLL being enabled for the device to operate correctly at cold
temperatures.
Resolution: Will be fixed in the next revision.
11. Description: Wake-up Timer and Low Duty Cycle Modes not functional.
Impacts: These features are not supported.
Workaround: Use the external microcontroller or the 32 kHz XTAL option on the RF22 to implement these
functions.
Resolution: Will be fixed in the next revision.
12. Description: In antenna diversity mode the antenna selected for the RX packet may not be the same as the
subsequent TX. The TX antenna selection will toggle between both antennas.
Impacts: May impact link performance depending on conditions.
Workaround: Customers can force the TX antenna control manually to a given antenna prior to sending the TX
packet by setting the ANTDIV[2:0] bits in register 08h.
Resolution: Will be fixed in the next revision.
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