RF42/43
Register 30h. Data Access Control
Bit
D7
Reserved
R/w
D6
lsbfrst
R/w
D5
crcdonly
R/w
D4
Reserved
R/w
D3
enpactx
R/w
D2
encrc
R/w
D1
D0
crc[1:0]
R/w
Name
Type
Reset value = 10001101
Bit
Name
Function
7
Reserved
Reserved.
LSB First Enable.
6
lsbfrst
The LSB of the data will be transmitted first if this bit is set.
CRC Data Only Enable.
5
4
crcdonly
When this bit is set to 1 the CRC is calculated on the packet data fields only.
Reserved.
Reserved
Enable Packet TX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be
enabled. Setting enpactx = 1 will enable automatic packet handling in the TX
path. Register 30–4D allow for various configurations of the packet structure.
Setting enpactx = 0 will not do any packet handling in the TX path. It will only
transmit what is loaded to the FIFO.
3
enpactx
CRC Enable.
2
encrc
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00:
01:
10:
11:
CCITT
1:0
crc[1:0]
CRC-16 (IBM)
IEC-16
Biacheva
76
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