RF42/43
3.5. System Timing
The system timing for TX mode is shown in Figure 6. The timing is shown transitioning from STANDBY mode to TX
mode and going automatically through the built-in sequencer of required steps. If a small range of frequencies is being
used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device.
The relevant system timing registers are shown below.
POR
Function/De
scription
D7
D6
D5
D4
D3
D2
D1
D0
Add R/W
Def.
45h
00h
R/W
PLL Tune Time
Reserved 1
Calibration
Control
pllts[4:0]
X
pllt0[2:0]
X
53
R/W
X
X
X
X
X
X
54
xtalstart
half
adccaldo
ne
Vcoca
ldp
R/W
enrcfcal
rccal
vcocal
skipvco
04h
55
The VCO will automatically calibrate at every frequency change or power up. The VCO CAL may also be forced by
setting the vcocal bit. The 32.768 kHz RC oscillator is also automatically calibrated but the calibration may also be
forced. The enrcfcal will enable the RC Fine Calibration which will occur every 30 seconds. The rccal bit will force a
complete calibration of the RC oscillator which will take approximately 2 ms. The PLL T0 time is to allow for bias
settling of the VCO, the default for this should be adequate. The PLL TS time is for the settling time of the PLL, which
has a default setting of 200 μs. This setting should be adequate for most applications but may be reduced if small
frequency jumps are used. For more information on the PLL register configuration options, see ―Register 53h. PLL
Tune Time,‖ and ―Register 55h. Calibration Control,‖.
Figure 6. TX Timing
19
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