RF42/43
Register 71h. Modulation Mode Control 2
Bit
D7
D6
D5
D4
dtmod[1:0]
R/W
D3
eninv
R/W
D2
D1
modtyp[1:0]
R/W
D0
trclk[1:0]
R/W
fd[8]
R/W
Name
Type
Reset value = 00000000
Bit
Name
Function
TX Data Clock Configuration.
00:
No TX Data CLK is available (asynchronous mode – Can only work with
modulations FSK or OOK).
trclk[1:0]
7:6
01:
TX Data CLK is available via the GPIO (one of the GPIO‘s should be
programmed as well).
10:
11:
TX Data CLK is available via the SDO pin.
TX Data CLK is available via the nIRQ pin.
Modulation Source.
00:
Direct Mode using TX_Data function via the GPIO pin (one of the GPIO‘s
should be programmed accordingly as well)
Direct Mode using TX_Data function via the SDI pin (only when nSEL is high)
FIFO Mode
dtmod[1:0]
5:4
01:
10:
11:
PN9 (internally generated)
eninv
fd[8]
3
2
TX Data.
MSB of Frequency Deviation Setting, see "Register 72h. Frequency
Deviation".
Modulation Type.
00:
01:
10:
11:
Unmodulated carrier
modtyp[1:0]
1：0
OOK
FSK
GFSK (enable TX Data CLK (trclk[1:0]) when direct mode is used)
The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0].
101
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