RF31
Register 2Eh. Slicer Peak Holder
Bit
D7
Reserved
R/w
D6
D5
attack[2:0]
R/w
D4
D3
D2
D1
D0
decay[3:0]
R/w
Name
Type
Reset value = 00101110
Bit
7
Name
Function
Reserved
attack[2:0]
decay[3:0]
Reserved.
6:4
3:0
Attack.
Decay.
Register 30h. Data Access Control
Bit
D7
enpacrx
R/w
D6
lsbfrst
R/w
D5
crcdonly
R/w
D4
Reserved
R/w
D3
D2
D1
D0
Reserved
encrc
R/w
crc[1:0]
R/w
Name
Type
R/w
Reset value = 00101100
Bit
Name
Function
Enable Packet RX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be
enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX
path. Register 30–4D allow for various configurations of the packet structure.
Setting enpacrx = 0 will not do any packet handling in the RX path. It will only
receive everything after the sync word and fill up the RX FIFO.
LSB First Enable.
enpacrx
7
lsbfrst
6
5
The LSB of the data will be received first if this bit is set.
CRC Data Only Enable.
crcdonly
When this bit is set to 1 the CRC is checked against the packet data fields only.
Reserved.
Reserved
Reserved
4
3
Reserved.
CRC Enable.
encrc
2
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00:
01:
10:
11:
CCITT
crc[1:0]
1:0
CRC-16 (IBM)
IEC-16
Biacheva
97
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