RF31
Register 08h. Operating Mode and Function Control 2
Bit
D7
D6
D5
D4
rxmpk
R/w
D3
Reserved
R/w
D2
enldm
R/w
D1
D0
Reserved
R/w
antdiv[2:0]
R/w
ffclrrx
R/w
Name
Type
Reset value = 00000001
Bit
Name
Function
Enable Antenna Diversity.
The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
RX state
non RX state
GPIO Ant1
GPIO Ant2
GPIO Ant1 GPIO Ant2
000:
001:
010:
011:
100:
101:
110:
111:
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
antdiv[2:0]
7:5
0
1
antenna diversity algorithm
antenna diversity algorithm
ant. div. algorithm in beacon mode
ant. div. algorithm in beacon mode
0
1
RX Multi Packet.
When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet
rxmpk
Reserved
enldm
4
3
2
Handling (enpacrx) then it will fill up the FIFO with multiple valid packets if this
bit is set, otherwise the receiver will automatically leave the RX State after the
first valid packet has been received.
Reserved.
Enable Low Duty Cycle Mode.
If this bit is set to 1 then the chip turns on the RX regularly. The frequency
should be set in the Wake-Up Timer Period register, while the minimum ON
time should be set in the Low-Duty Cycle Mode Duration register. The FIFO
mode should be enabled also.
RX FIFO Reset/Clear.
ffclrrx
1
0
This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0
will clear the contents of the RX FIFO.
Reserved
Reserved.
75
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