RF31
3.3. Interrupts
The RF31 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt
signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits)
shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s)
(Registers 03h–04h) containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the
next change in status is detected. All of the interrupts must be enabled by the corresponding enable bit in the
Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller
reads the interrupt status register. If the interrupt is not enabled when the event occurs inside of the chip it will not
trigger the nIRQ pin, but the status may still be read correctly at anytime in the Interrupt Status registers.
POR
Def.
Function/De
scription
D7
D6
D5
D4
D3
D2
D1
D0
Add R/W
R
Interrupt Status 1
Interrupt Status 2
ifferr
Reserved
ipreaval
Reserved
ipreainval
irxffafull
irssi
iext
Reserved
ilbd
ipkvalid
ichiprdy
icrcerror
ipor
—
03
R
iswdet
iwut
—
04
encrcerr
or
R/W
Interrupt Enable1
enfferr
Reserved
Reserved
enrxffafull
enrssi
enext
enwut
Reserved enpkvalid
enlbd enchiprdy
00h
05
R/W
Interrupt Enable 2 enswdet
enpreaval enpreainval
enpor
01h
06
See ―Register 03h. Interrupt/Status 1,‖ and ―Register 04h. Interrupt/Status 2,‖ for a complete list of interrupts.
3.4. Device Code
The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Notes
Add R/W Function/Description
01
R
Device Version
0
0
0
vc[4]
vc[3] vc[2] vc[1] vc[0]
00h
DV
19
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