HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINAand RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
TEST
ONE
S
Q
ROUTA
LATCH
R
TEST
'
TESTA TESTB
TESTA
RINA
ESD
NULL
PROTECTION
AND
TEST
TRANSLATION
ZERO
RINB
S
Q
ROUTB
LATCH
R
TEST
'
TESTA TESTB
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
VCC
2
6
7
HARDWIRE
OR
DRIVE FROM LOGIC
TESTA
TESTB
ROUTA
ROUTB
RXD1
RXD0
8
{
HI-8588
4
RINA
ARINC
Channel
HI-6010
3
APPLICATION INFORMATION
RINB
5
Figure 2 shows a possible application
of the HI-8588 interfacing anARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
8 BIT BUS
15V
1
SLP1.5 V+
8
6
7
3
2
TXD1
TXD0
TXAOUT TX1IN
ARINC
Channel
HI-8586
TXBOUT
TX0IN
GND
V-
5
4
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
