HI-8581
Vcc = 5V, V+=10V, V- = -10V, GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
LIMITS
PARAMETER
CONTROL WORD TIMING
SYMBOL
UNITS
MIN
TYP
MAX
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
50
50
0
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
ns
ns
200
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
tSELEN
tENSEL
0
0
ns
ns
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
50
50
80
30
ns
ns
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tEN
tENEN
80
50
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
tPL
50
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
50
0
ns
ns
Spacing - PL1 or PL2
tPL12
tTX/R
0
ns
ns
Delay - PL2 HIGH to TX/R LOW
840
50
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX L0W
tPL2EN
tDTX/R
0
0
µs
ns
ns
tENTX/R
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
tENDAT
tENDAT
25
200
µs
µs
Line driver transition differential times:
(High Speed)
high to low
low to high
t
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
fx
t
rx
(Low Speed)
high to low
low to high
t
5.0
5.0
10
10
15
15
µs
µs
fx
t
rx
HOLT INTEGRATED CIRCUITS
11