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HI-8282UT 参数 Datasheet PDF下载

HI-8282UT图片预览
型号: HI-8282UT
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429串行发送器和双接收机 [ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER]
分类和应用: 接收机
文件页数/大小: 14 页 / 451 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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ARINC 429 DATA FORMAT  
FUNCTIONAL DESCRIPTION  
The following table shows the bit positions in exchanging data with  
the receiver or the transmitter. ARINC bit 1 is the first bit  
transmitted or received.  
CONTROL WORD REGISTER  
The HI-8282 contains 10 data flip flops whose D inputs are con-  
nected to the data bus and clocks connected to CWSTR . Each  
flip flop provides options to the user as follows:  
BYTE 1  
DATA  
BUS  
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD  
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
DATA  
BUS  
PIN  
ARINC  
BIT  
13 12 11 10  
9
31 30 32  
1
2
3
4
5
6
7
8
FUNCTION CONTROL  
DESCRIPTION  
If enabled, an internal connection  
is made passing 429DO and  
429DO to the receiver logic inputs  
BYTE 2  
BDO5  
BDO6  
BDO7  
BDO8  
BDO9  
BD10  
BD11  
SELF TEST 0 = ENABLE  
RECEIVER 1  
DATA  
BUS  
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD  
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
If enabled, ARINC bits 9 and,  
10 must match the next two  
control word bits  
DECODER  
1 = ENABLE  
ARINC  
BIT  
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14  
If Receiver 1 Decoder is  
enabled, the ARINC bit 9  
must match this bit  
-
-
-
THE RECEIVERS  
If Receiver 1 Decoder is  
enabled, the ARINC bit 10  
must match this bit  
ARINC BUS INTERFACE  
-
Figure 1 shows the input circuit for each receiver. The ARINC 429  
specification requires the following detection levels:  
RECEIVER 2  
DECODER  
If enabled, ARINC bits 9 and  
10 must match the next two  
control word bits  
1 = ENABLE  
STATE  
DIFFERENTIAL VOLTAGE  
If Receiver 2 Decoder is  
enabled, then ARINC bit 9  
must match this bit  
ONE  
NULL  
ZERO  
+6.5 Volts to +13 Volts  
+2.5 Volts to -2.5 Volts  
-6.5 Volts to -13 Volts  
-
-
-
-
If Receiver 2 Decoder is  
enabled, then ARIN C bit 10  
must match this bit  
The HI-8282 guarantees recognition of these levels with a common  
mode Voltage with respect to GND less than ±4V for the worst case  
condition (4.75V supply and 13v signal level).  
INVERT  
XMTR  
PARITY  
Logic 0 enables normal odd parity  
1 = ENABLE and Logic 1 enables even parity  
output in transmitter 32nd bit  
BD12  
BD13  
BD14  
The tolerances in the design guarantee detection of the above  
levels, so the actual acceptance ranges are slightly larger. If the  
ARINC signal is out of the actual acceptance ranges, including the  
nulls, the chip rejects the data.  
XMTR DATA  
CLK SELECT  
0 = ÷10  
1 = ÷80  
CLK is divided either by 10 or  
80 to obtain XMTR data clock  
RCVR DTA  
CLK SELECT  
0 = ÷10  
1 = ÷80  
CLK is divided either by 10 or  
80 to obtain RCVR data clock  
HOLT INTEGRATED CIRCUITS  
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