HI-8282A
ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
January 2006
GENERALDESCRIPTION
FEATURES
! ARINC specification 429 compliant
The HI-8282A is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet theARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
Additional interface circuitry such as the Holt HI-8585,
HI-8586 or HI-3182 is required to translate the 5 volt logic
outputs toARINC 429 drive levels.
! Alternate source to Intersil HS-3282 in all
ARINC 429 applications
! Small footprint 44-pin QFP package option
! 16-Bit parallel data bus
! Direct receiver interface to ARINC bus
! Timing control 10 times the data rate
! Selectable data clocks
! Automatic transmitter data timing
! 8 word transmit FIFO
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS andTTL.
! Receiver error rejection per ARINC
specification 429
! Self test mode
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
! Parity functions
! Low power, single 5 volt supply
! Industrial & full military temperature ranges
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282A examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
PIN CONFIGURATION (Top View)
The transmitter has a First In, First Out (FIFO) memory to
store 8ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of theARINC transmission within the required
resolution.
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 - 429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
HI-8282APQI
HI-8282APQT
HI-8282APQM
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional Package Pin Configurations)
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8282A Rev. E)
01/06
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
