HI-3584A
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle
LIMITS
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
25
25
5
ns
ns
ns
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
Delay - D/R LOW to EN LOW
Delay - EN HIGH to D/R HIGH
tD/REN
tEND/R
0
ns
ns
25
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
tSELEN
tENSEL
0
10
ns
ns
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
50
20
ns
ns
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW (Same ARINC Word)
Spacing -EN HIGH to next EN LOW (Next ARINC Word)
CLK HIGH separation from second EN pulse HIGH (SEL is HIGH)
tEN
tENEN
tREADEN
tCLKEN
50
70
70
25
ns
ns
ns
ns
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - Pl1 or PL2
tPL
30
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
30
10
ns
ns
Spacing - PL1 or PL2
Spacing - PL1 rising to PL2 rising
Spacing between Label Write pulses
tPL12
tPLCYC
tLABEL
40
40
ns
ns
ns
tCLK-10
30
Delay - PL2 HIGH to TX/R LOW
tTX/R
ns
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
tPL2EN
tDTX/R
0
0
µs
ns
ns
µs
µs
50
Spacing - TX/R HIGH to ENTX LOW
tENTX/R
tENDAT
tENDAT
Delay - ENTX HIGH to 429DO or 429DO: High Speed
Delay - ENTX HIGH to 429DO or 429DO: Low Speed
25
200
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
tPLEN
tTX/REN
tMR
0
0
ns
ns
ns
ns
Hold - PL HIGH to EN HIGH
Delay - TX/R LOW to ENTX HIGH
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
0
175
1%
HOLT INTEGRATED CIRCUITS
12
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
