HI-3582A, HI-3583A
TIMING DIAGRAMS (cont.)
STATUS REGISTER READ CYCLE
BYTE SELECT
SEL
DON'T CARE
DON'T CARE
t
SELEN
RSR
t
ENSEL
t
DATAEN
DATA BUS
DATA VALID
t
ENDATA
CONTROL REGISTER READ CYCLE
BYTE SELECT
SEL
DON'T CARE
DON'T CARE
t
SELEN
RSR
t
ENSEL
t
DATAEN
DATA BUS
DATA VALID
t
ENDATA
LABEL MEMORY LOAD SEQUENCE
t
CWSTR
CWSTR
t
CWSET
DATA BUS
Set CR1=1
t
CWHLD
Label #1
Label #2
Label #16
Set CR1=0
t
DWSET
t
DWHLD
PL1 or PL2
t
PL
t
LABEL
LABEL MEMORY READ SEQUENCE
t
CWSTR
CWSTR
t
READEN
EN1 or EN2
t
CWHLD
t
CWSET
DATA BUS
Set CR1=1
Label #1
t
DATAEN
Label #2
Label #16
Set CR1=0
t
ENDATA
HOLT INTEGRATED CIRCUITS
9