HI-3582A, HI-3583A
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle
PARAMETER
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
Delay - D/R LOW to EN LOW
Delay - EN HIGH to D/R HIGH
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW (Same ARINC Word)
Spacing -EN HIGH to next EN LOW (Next ARINC Word)
CLK HIGH separation from second EN pulse HIGH (SEL is HIGH)
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
Spacing - PL1 or PL2
Spacing - PL1 rising to PL2 rising
Spacing between Label Write pulses
Delay - PL2 HIGH to TX/R LOW
Delay - PL2 HIGH to HFT low
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX LOW
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed
Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0)
(Low Speed, control register CR13 = Logic 1)
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
Hold - PL HIGH to EN HIGH
Delay - TX/R LOW to ENTX HIGH
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
high to low
low to high
high to low
low to high
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
t
CWSTR
t
CWSET
t
CWHLD
25
25
5
ns
ns
ns
t
D/R
t
D/R
t
D/REN
t
END/R
t
SELEN
t
ENSEL
t
ENDATA
t
DATAEN
t
EN
t
ENEN
t
READEN
t
CLKEN
50
70
70
25
0
16
128
25
0
10
50
20
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PL
t
DWSET
t
DWHLD
t
PL12
t
PLCYC
t
LABEL
t
TX/R
t
HFT
30
30
10
40
t
CLK
-10
40
30
25
ns
ns
ns
ns
ns
ns
ns
ns
t
PL2EN
t
DTX/R
t
ENTX/R
0
50
0
ns
ns
ns
t
ENDAT
t
ENDAT
t
fx
t
rx
t
fx
t
rx
1.0
1.0
5.0
5.0
1.5
1.5
10
10
25
200
2.0
2.0
15
15
µs
µs
µs
µs
µs
µs
t
ENPL
t
PLEN
t
TX/REN
t
MR
0
0
0
175
± 1%
ns
ns
ns
ns
HOLT INTEGRATED CIRCUITS
13
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
