HI-3210
HI-3210 Operational Status Information
The Master Status Register may be read at any time to determine the current operational state of the HI-3210:
X
1
X
MASTER STATUS REGISTER
(Address 0x800E)
7
6
5
4
3
2
0
LSB
MSB
Bit Name
R/W Default Description
7
READY
R
0
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
6
5
ACTIVE
SAFE
R
R
0
0
This bit is high after RUN is asserted and the HI-3210 is in normal operating mode.
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto-
initialization fail.
4
3
RAM BUSY
PROG
R
R
0
0
This is high during the time the RAM Integrity Check is running and RAM is clearing
Indicates that the HI-3210 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
2
AUTOINIT
R
0
The HI-3210 is currently loading internal memory, registers and look-up tables from the Auto-
initialization EEPROM
1
0
-
-
R
R
0
0
Not used
Not Used
HOLT INTEGRATED CIRCUITS
11
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
