HI-3210
HI-3210 Operational Status Information
The Master Status Register may be read at any time to determine the current operational state of the HI-3210:
EA
AC DY
T
SA IVE
F
R E
AM
PR BU
O S
AU G Y
TO
IN
IT
X
7 6
MSB
5
4
3
2
1
X
0
LSB
MASTER STATUS REGISTER
(Address 0x800E)
Bit Name
7
6
5
4
3
2
1
0
READY
ACTIVE
SAFE
RAM BUSY
PROG
AUTOINIT
-
-
R/W
R
R
R
R
R
R
R
R
Default Description
0
0
0
0
0
0
0
0
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
This bit is high after RUN is asserted and the HI-3210 is in normal operating mode.
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto-
initialization fail.
This is high during the time the RAM Integrity Check is running and RAM is clearing
Indicates that the HI-3210 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
The HI-3210 is currently loading internal memory, registers and look-up tables from the Auto-
initialization EEPROM
Not used
Not Used
HOLT INTEGRATED CIRCUITS
11
R
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
