HI-3210
Example 2. ARINC 429 Data reception using on-chip filters and FIFOs
FILTER
TABLE 0
RECEIVER 0
LABEL
FILTER
Message 32
“
“
“
Message 2
Message 1
8 x ARINC 429
Receive Buses
32 x 32 FIFO
SPI
FIFO STATUS
HCSB
HSCLK
HMOSI
HMISO
Host CPU
FIFO EMPTY
FIFO THRESHOLD
FIFO FULL
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
ARINC 429
RECEIVE FIFO
INTERRUPT
CONTROL
AINT
AACK
HI-3210
Example 3. ARINC 429 Data transmission directly from CPU
TRANSMITTER 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
TRANSMITTER 1
SPI
TRANSMITTER 2
4 x ARINC 429
Transmit Buses
TRANSMITTER 3
HI-3210
Example 4. ARINC 429 Data transmission using on-chip schedulers
Descriptor Table 0
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
Host CPU
HCSB
HSCLK
HMOSI
HMISO
SPI
Descriptor Table 1
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
4 x ARINC 429
Transmit Buses
Descriptor Table 2
Auto-Initialization
EEPROM
ECSB
ESCLK
EMOSI
EMISO
EEPROM
SPI
Descriptor Table 3
RAM
HI-3210
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
