HI-3210
HI-3210 SYSTEM CONFIGURATION
Starting at memory address 0x8000, the HI-3210
contains a set of registers that are used to configure the
device.
The user needs only to program the HI-3210
configuration registers to completely define the full
system operation.
The configuration registers are divided into three
categories, as follows;
1. HI-3210 global configuration
2. ARINC 429 Receive channel configuration
3. ARINC 429 Transmit channel configuration
HI-3210 Global Configuration
The following registers define the HI-3210 top-level configuration:
A4
29
A4 R X
29
TX
AF
LI
0
4
3
X
2
X
1
MASTER CONTROL REGISTER
(Address 0x800F)
Bit Name
7
A429RX
R/W
R/W
Default Description
0
0
7 6
MSB
5
P
X
0
LSB
This bit must be set to a “1” to allow the HI-3210 to receive ARINC 429 data on any of the eight
channels. If set to a zero, the HI-3210 will not respond to any ARINC 429 receive bus,
regardless of the state of the ARINC 429 Receive channel Control Registers.
This bit must be set to a “1” to allow the HI-3210 to transmit ARINC 429 data on any of the four
channels. If set to a zero, the HI-3210 will not output ARINC 429 data and the ARINC 429
transmit sequencers will remain in their reset state.
Must be ‘0’
Must be ‘0’
When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and
transmit channels.
Not Used
Not Used
Not Used
6
A429TX
R/W
0
5
4
3
2
1
0
-
-
AFLIP
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
HOLT INTEGRATED CIRCUITS
10
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
