HI-3282, HI-3282B
FUNCTIONAL DESCRIPTION (cont.)
REPEATER OPERATION
The repeater mode of operation allows a data word that has been
received by the HI-3282 to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shift register, the D/R flag will go low. A logic "0" is placed on the SEL
line and EN is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on the data bus. By strobing PL1 at the same time as EN, the byte
will also be placed into the transmitter FIFO. SEL is then taken high
and EN is strobed again to place the upper byte of the data word on
the data bus. By strobing PL2 at the same time as EN, the second
byte will also be placed into the FIFO. The data word is now ready to
be transmitted according to the parity programmed into the control
word register.
In normal operation, either byte of a received data word may be read
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loaded with the lower byte of the data word first.
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
429DO
ARINC BIT
429DO
DATA
NULL
DATA
NULL
DATA
NULL
BIT 30
BIT 31
BIT 32
WORD GAP
BIT 1
NEXT WORD
LOADING CONTROL WORD
DATA BUS
VALID
t
CWSET
t
CWHLD
CWSTR
t
CWSTR
RECEIVER OPERATON
ARINC DATA
BIT 31
BIT 32
DATA READY FLAG
D/R
t
D/R
BYTE SELECT
SEL
DON'T CARE
DON'T CARE
t
END/R
t
EN
t
SELEN
t
ENEN
t
DATAEN
BYTE 1 VALID
BYTE 2 VALID
DON'T CARE
t
SELEN
ENABLE BYTE ON BUS
EN
t
ENSEL
t
ENSEL
t
D/REN
DATA BUS
t
DATAEN
t
ENDATA
t
ENDATA
HOLT INTEGRATED CIRCUITS
6
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
