HI-3200, HI-3201
HI-3200 REGISTER MAP
ADDRESS R/W
REGISTER
MNEMONIC DESCRIPTION
0x8000
0x8001
0x8002
0x8003
0x8004
0x8005
0x8006
0x8007
0x8008
0x8009
0x800A
0x800B
0x800C
0x800D
0x800E
0x800F
R*
R
ARINC 429 Rx PENDING INTERRUPT
ARINC 429 Rx INTERRUPT ADDRESS 0
ARINC 429 Rx INTERRUPT ADDRESS 1
ARINC 429 Rx INTERRUPT ADDRESS 2
ARINC 429 Rx INTERRUPT ADDRESS 3
ARINC 429 Rx INTERRUPT ADDRESS 4
ARINC 429 Rx INTERRUPT ADDRESS 5
ARINC 429 Rx INTERRUPT ADDRESS 6
ARINC 429 Rx INTERRUPT ADDRESS 7
RESERVED
APIR
AIAR0
AIAR1
AIAR2
AIAR3
AIAR4
AIAR5
AIAR6
AIAR7
Defines channel(s) with pending Interrupt
ARINC 429 Interrupt Vector channel 0
ARINC 429 Interrupt Vector channel 1
ARINC 429 Interrupt Vector channel 2
ARINC 429 Interrupt Vector channel 3
ARINC 429 Interrupt Vector channel 4
ARINC 429 Interrupt Vector channel 5
ARINC 429 Interrupt Vector channel 6
ARINC 429 Interrupt Vector channel 7
R
R
R
R
R
R
R
-
R*
R
PENDING INTERRUPT REGISTER
INTERRUPT ADDRESS REGISTER
MUXED FIFO FLAGS
PIR
CIAR
AMFF
ATRB
MSR
MCR
Indicates Interrupt type
CAN bus Interrupt vector
R
ARINC 429 Multiplexed FIFO flags
ARINC 429 Transmitter Ready flags
Indicates HI-3200 current status
HI-3200 global configuration
R
ARINC 429 TX READY BITS
R
MASTER STATUS REGISTER
R/W
MASTER CONTROL REGISTER
0x8010
0x8011
0x8012
0x8013
0x8014
0x8015
0x8016
0x8017
0x8018
0x8019
0x801A
0x801B
0x801C
0x801D
0x801E
0x801F
0x8020
0x8021
0x8022
0x8029
0x802A
0x802B
0x802C
0x802D
0x802E
0x802F
0x8030
0x8031
0x8032
0x8033
0x8034
0x8035
0x803E
0x803F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ARINC 429 RX CONTROL REGISTER 0
ARINC 429 RX CONTROL REGISTER 1
ARINC 429 RX CONTROL REGISTER 2
ARINC 429 RX CONTROL REGISTER 3
ARINC 429 RX CONTROL REGISTER 4
ARINC 429 RX CONTROL REGISTER 5
ARINC 429 RX CONTROL REGISTER 6
ARINC 429 RX CONTROL REGISTER 7
ARINC 429 TX CONTROL REGISTER 0
ARINC 429 TX CONTROL REGISTER 1
ARINC 429 TX CONTROL REGISTER 2
ARINC 429 TX CONTROL REGISTER 3
ARINC 429 TX REPETITION RATE 0
ARINC 429 TX REPETITION RATE 1
ARINC 429 TX REPETITION RATE 2
ARINC 429 TX REPETITION RATE 3
ARINC 429 Rx INTERRUPT MASK
ARXC0
ARXC1
ARXC2
ARXC3
ARXC4
ARXC5
ARXC6
ARXC7
ATXC0
Configures ARINC 429 receive channel 0
Configures ARINC 429 receive channel 1
Configures ARINC 429 receive channel 2
Configures ARINC 429 receive channel 3
Configures ARINC 429 receive channel 4
Configures ARINC 429 receive channel 5
Configures ARINC 429 receive channel 6
Configures ARINC 429 receive channel 7
Configures ARINC 429 transmit channel 0
Configures ARINC 429 transmit channel 1
Configures ARINC 429 transmit channel 2
Configures ARINC 429 transmit channel 3
Sets sequence repeat time for ARINC TX0
Sets sequence repeat time for ARINC TX1
Sets sequence repeat time for ARINC TX2
Sets sequence repeat time for ARINC TX3
Enables Interrupts on AINT pin
ATXC1
ATXC2
ATXC3
ATXRR0
ATXRR1
ATXRR2
ATXRR3
AIMR
R/W ARINC 429 Rx FIFO THRESHOLD VALUE
AFTV
Sets flag value for ARINC 429 Receive FIFO
Sets loop-back self-test mode
R/W
R
ARINC 429 LOOPBACK
ALOOP
AFFF
ARINC 429 Rx FIFO FULL FLAG
Indicates which FIFOs are full
R
ARINC 429 Rx FIFO THRESHOLD FLAG
ARINC 429 Rx FIFO NOT EMPTY FLAG
ARINC 429 TX SEQUENCE POINTER 0
ARINC 429 TX SEQUENCE POINTER 1
ARINC 429 TX SEQUENCE POINTER 2
ARINC 429 TX SEQUENCE POINTER 3
CAN BUS BIT TIMING REGISTER 0
CAN BUS BIT TIMING REGISTER 1
CAN TRANSMIT CONTROL REGISTER
CAN TX REPETITION RATE
AFTF
Indicates which FIFOs hold > (thresh) messages
Indicates which receive FIFOs hold data
Current address of ARINC transmit sequence 0
Current address of ARINC transmit sequence 1
Current address of ARINC transmit sequence 2
Current address of ARINC transmit sequence 3
Sets bit timing parameters for CAN bus
Sets bit timing parameters for CAN bus
Controls CAN bus transmit scheduler
R
FFNE
R
ATXSP0
ATXSP1
ATXSP2
ATXSP3
CANBTR0
CANBTR1
CANTXC
CANTXRR
IMR
R
R
R
R/W
R/W
R/W
R/W
Sets sequence repeat time for CAN transmitter
Enables Interrupts on MINT pin
R/W PENDING INTERRUPT ENABLE REGISTER
R/W
R
ARINC 429 TX READY INT ENABLE
CAN TX SEQUENCE POINTER MSB
CAN TX SEQUENCE POINTER LSB
ATRIE
Enables ARINC 429 TX Ready Interrupts
High order CAN transmit sequence counter
Low order CAN transmit sequence counter
CANTXSPH
CANTXSPL
R
Fast Access Registers
Memory mapped register access only
HOLT INTEGRATED CIRCUITS
10
* Register is cleared when read (auto clear)
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
