HI-3200, HI-3201
BLOCK DIAGRAM
Host CPU
MINTACK
MINT
ARINC 429
BIT MATCH
ARXBIT7
ARXBIT6
ARXBIT5
ARXBIT4
ARXBIT3
ARXBIT2
ARXBIT1
ARXBIT0
ARINC 429
RECEIVE DATA
MEMORY 0
1K x 8
HCSB
HSCLK
HMOSI
HMISO
ARINC 429
Interrupt Handler
AACK
AINT
SPI
ARINC 825 (CAN)
Interrupt Handler
8 x ARINC 429 Receive Buses
RECEIVER 0
FILTER
TABLE 0
ARINC 825 (CAN)
Descriptor Table
ARINC 825 (CAN)
TRANSMIT
SCHEDULER
32 x 32 FIFO
TRANSMIT TIMER
LABEL
FILTER
HI-3110
Data
Interfacel
ARINC 825 / CAN
FILTER / MASK
TABLE
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
HI-3110
Configuration
& Control
CMROUT
COSC
CGP2
CSTAT
ARINC825 / CAN
RECEIVE DATA
MEMORY
4K x 8
ARINC 825 (CAN)
FILTER
HI-3110
Transceiver
4 x ARINC 429 Transmit Buses
TRANSMITTER 0
ARINC 429
TRANSMIT
SCHEDULER 0
ARINC 429
Descriptor Table 0
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
EEPROM
SPI
HI-3200
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
2
ECSB
ESCLK
EMOSI
EMISO
ARINC 825 / CAN Bus
Message 32
“
“
“
Message 2
Message 1
CCSB
CSCLK
CMOSI
CMISO
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
