HI-3200, HI-3201
HI-3200 SYSTEM CONFIGURATION
Starting at memory address 0x8000, the HI-3200
contains a set of registers that are used to configure the
HI-3200 device and, if used, its associated HI-3110
integrated CAN controller / transceiver.
An SPI by-pass mode allows the user to directly access
the HI-3110, but it is highly recommended that this is
used solely for design debugging purposes and is locked
out in the final design implementation. By-pass mode is
enabled by setting the state of the MODE2:0 pins during
reset. See the Reset and Start-Up Configuration section
for more details.
The user needs only to program the HI-3200
configuration registers to completely define the full
system operation.
The configuration registers are divided into four
categories, as follows;
Configuration information for the HI-3110 is automatically
transferred from the HI-3200 to the HI-3110 immediately
after the RUN input is asserted.
1. HI-3200 global configuration
2. ARINC 429 Receive channel configuration
3. ARINC 429 Transmit channel configuration
4. CAN Bus bit timing configuration
HI-3200 Global Configuration
The following registers define the HI-3200 top-level configuration:
X
2
X
1
X
MASTER CONTROL REGISTER
(Address 0x800F)
7
6
5
4
3
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
A429RX
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
This bit must be set to a “1” to allow the HI-3200 to receiveARINC 429 data on any of the eight
channels. If set to a zero, the HI-3200 will not respond to any ARINC 429 receive bus,
regardless of the state of theARINC 429 Receive channel Control Registers.
A429TX
CANRX
CANTX
AFLIP
This bit must be set to a “1” to allow the HI-3200 to transmit ARINC 429 data on any of the four
channels. If set to a zero, the HI-3200 will not output ARINC 429 data and the ARINC 429
transmit sequencers will remain in their reset state.
This bit must be set to a “1” to allow the HI-3200 to receive CAN Frames from the HI-3110
controller. If set to a zero, the HI-3200 will not respond to any received CAN frames, regardless
of the state of the CAN Bus Control Register.
This bit must be set to a “1” to allow the HI-3200 to transmit CAN frames. If set to a zero, the
HI-3200 will not output CAN frames and the CAN transmit sequencer will remain in its reset
state.
When set to a “1”, this bit switches the bit order of theARINC 429 label byte in both receive and
transmit channels.
2
1
0
-
-
-
R/W
R/W
R/W
0
0
0
Not Used
Not Used
Not Used
HOLT INTEGRATED CIRCUITS
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HOLTIC [ HOLT INTEGRATED CIRCUITS ]
