HI-3189
PIN DESCRIPTIONS
SYMBOL
VREF
RATE SELECT
SYNC
DATA (A)
CAPA
OUTA
-VS
GND
+VS
AMPA
OUTB
CAPB
DATA (B)
CLOCK
AMPB
VLOGIC
FUNCTION
ANALOG
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
POWER
POWER
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
DESCRIPTION
Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference.
Selects ARINC 429 data rate. See Table 2 for operation.
Synchronizes data inputs
Data input terminal A
Connection for DATA (A) slew-rate capacitor
ARINC output terminal A with 37.5 Ohms internal series resistance
-15V ± 10%
0.0V
+15V ± 10%
ARINC output terminal A with 0 Ohms internal series resistance
ARINC output terminal B with 37.5 Ohms internal series resistance
Connection for DATA (B) slew-rate capacitor
Data input terminal B
Synchronizes data inputs
ARINC output terminal B with 0 Ohms internal series resistance
+5V ±10%
Rate Select
Logic “0”
Logic “1”
Logic “0”
Logic “1”
CAPA, CAPB
Value (pF)
68
68
470
470
Rise / Fall Time
10% - 90% (us)
1.0 - 2.0
5.0 - 15.0
5.0 - 15.0
N/A
Data Rate
(Kbits/sec)
100
12.0 - 14.5
12.0 - 14.5
N/A
Comments
ARINC 429 High-Speed
ARINC 429 Low-Speed
ARINC 429 Low-Speed
Not Used
Table 2. Rate Select Pin Truth Table
VREF
+VS
CAPA
OUTPUT
DRIVER (A)
DATA (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
+VS
37.5W
AMPA
OUTA
CLOCK
RATE SELECT
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
OUTPUT
DRIVER (B)
-VS
+VS
37.5W
OUTB
C
L
R
L
DATA (B)
-VS
AMPB
GND
-VS
CAPB
Figure 2. Functional Block Diagram
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
