HI-3110
FUNCTIONAL OVERVIEW
The HI-3110 is the first single chip product to integrate both
the CAN (Controller Area Network) protocol and analog
interface transceiver on a single IC. The protocol conforms
to CAN version 2.0B and is compliant with ISO 11898-
1:2003(E) specification. The transceiver is compliant with
ISO 11898-5 specification.
Configuration options include an internal Loopback mode
that does not disturb the bus, a Monitor only mode, and a
Sleep mode that includes an option to either wake up
automatically when data is present on the bus, or by host
command. The following sections describe some of the key
features.
SPI and REGISTERS
To minimize the footprint, a 20 MHz standard four wire SPI
(Serial Peripheral Interface) is provided to manage the flow
of data between the host microcontroller and the HI-3110.
Complete messages are loaded and retrieved with single
SPI op codes. On the receive side, SPI op code options may
be used to retrieve the whole message or just the data. An
option to include a time tag or no time tag may also be
specified. On the transmit side, each message can be
assigned an identifier which allows monitoring of the
Transmit History FIFO to confirm the successful completion
of a transmission along with the time stamp. In addition the
transmitter logic automatically assembles the message
frame based on the data presented.
BIT TIMING
Bit timing is controlled with standard CAN options. These
include control of the Resychronization Jump Width (SJW),
Prop delay Phase Seg 1 (TSeg1), Phase Seg 2 (TSeg2), the
number of samples, and the derivation of Tq from the system
clock using a prescaler. The maximum bit rate is 1 MBit/sec.
Upon reset, the chip automatically enters Initialization mode
which allows programming of the Bit Timing before entering
Normal mode.
TRANSMITTER
The transmitter state machine automatically handles all
CAN 2.0B protocol requirements. Messages for
transmission are first loaded into a FIFO and transmission
may start upon availability of data in the FIFO. Assertion of
the TXEN pin or configuration bits in Control Register 1 allow
either continuous transmission until the FIFO is empty or
only one message from the FIFO at a time. One shot (no
retry) transmission may also be enabled by setting the OSM
bit. SPI op codes are provided to clear the Transmit FIFO
and to abort transmission.
RECEIVER
The receiver state machine automatically handles all CAN
2.0B protocol requirements. The receiver supports eight
sets of filters and masks and each allows filtering of a full
CAN ID (extended or not) and two bytes of data. Even when
filtering is enabled, message data is always accessible as
received via the Temporary Receive Buffer, and retrievable
by SPI op codes 0x42 and 0x44.
If the Filter/Mask option is set (FILTON bit in Control Register
1), only messages that match one of the 8 stored data
patterns are passed into the FIFO. Note that the Mask option
allows certain bits of the programmed filter bits to be “don't
care.” If the Filter/Mask option is not set, then all valid
messages are passed to the FIFO. When the FIFO is full (8
completed messages received), the next received message
is not loaded in the FIFO.
ERROR CONTROL
Errors are detected per ISO 11898-1:2003(E) and
detections are counted and used by the protocol state
machines. Active, Passive, and Bus Off conditions are
managed per the CAN standard. A configuration bit is
provided to allow automatic recovery from Bus Off.
STATUS and INTERRUPTS
The Message Status Register, MESSTAT, provides
information about the current state of the receiver and
transmitter operation. In addition, the Interrupt Flag
Register, INTF, monitors 8 operational conditions, any or all
of which may be directed to the INT pin by enabling bits in the
Interrupt Enable Register, INTE. Similarly, the Status Flag
Register, STATF, bits reflect the status of selected FIFO and
Error properties. Any or all of these conditions may be
directed to the STAT pin by setting the enable bits in the
Status Flag Enable Register, STATFE.
To provide additional hardwired flag options, the GP1 and
GP2 pins may also be programmed to reflect any of the
Interrupt or Status Flag bits.
OSCILLATOR and TIME TAG
A configuration bit allows a choice for the source of the
system clock. Either the on-board crystal oscillator may be
selected or an external clock may be provided at the OSCIN
pin.
On product versions with the CLKOUT pin, a programmable
division of the system clock is provided. The clock source for
the 16 bit Time Tag Counter is derived from a separate
programmable division of the system clock. SPI op codes
provide for reading and resetting the Time Tag Counter.
HOLT INTEGRATED CIRCUITS
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HOLTIC [ HOLT INTEGRATED CIRCUITS ]
