HI-3110
CONTROL REGISTER 0: CTRL0
MODE
M
1
ODE0
TTDIVT1TDIV0
(Write, SPI Op-code 0x14)
(Read, SPI Op-code 0xD2)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
R/W 1,0,0 Mode select bits <2:0>.
7-5 MODE2:0
These bits select the mode of operation as follows.
000: Normal Mode.
001: Loopback Mode.
Normal CAN operation.
The transceiver digital input is fed back to the receiver without
disturbing the bus. This mode can be used for test purposes,
allowing the HI-3110 to receive its own messages.
010: Monitor Mode.
011: Sleep Mode.
The HI-3110 can be set up to monitor bus activity without
transmitting to the bus (noACK bits or error frames are sent in this
mode). Receive filters can be programmed in Initialization Mode to
buffer selected messages.
The HI-3110 can be placed in a low power sleep mode if there is no
bus activity and the transmit FIFO is empty. Sleep mode is exited
by selecting an alternative mode of operation, or automatic wake
up following bus activity can be enabled by setting the WAKEUP
bit. The device will wake up in Monitor mode.
1xx: Initialization Mode. The device must be in this mode for bit timing and filter set-up.
This is the default following reset. The host exits initialization
mode by selecting an alternative mode of operation.
4
WAKEUP
R/W
0
Wake-Up Enable.
When this bit is set, the HI-3110 will automatically wake up from Sleep Mode to Monitor Mode
when it detects activity on the bus.
1
=
Automatic wake-up enabled. When the device wakes up from
Sleep Mode, the WAKEUPbit will be set in the Interrupt Flag
Register, INTF. Ahardware interrupt can be generated at the INT
pin by setting the WAKEUPIE bit in the Interrupt Enable Register.
Automatic wake-up not enabled. In this case, wake-up from Sleep
Mode is initiated by the host by selecting another mode of
operation. When WAKEUP= 0, all bus activity is ignored.
0
=
3
2
RESET
BOR
R/W
R/W
0
0
Setting this bit causes HI-3110 reset to occur. The bit should then be cleared by writing a logic
“0” following reset.Areset may also be performed by setting the MR pin or issuing the “MR” SPI
command, 0x56.
1
0
=
=
Master Reset (same as MR pin = 1).
Normal Operation (same as MR pin = 0).
Bus-off Reset.
When this bit is set, automatic bus-off recovery is initiated following 128 occurrences of 11
consecutive recessive bits on the bus. The HI-3110 will become error-active with both its error
counters set to zero and resume operation in Normal Mode.
1
0
=
=
Automatic bus-off recovery.
The host is responsible for bus-off recovery (default).
1-0 TDIV1:0
R/W
0,0
TimeTag Clock Division Bits <1:0>. SeeTIMERUB andTIMERLB register descriptions.
00 =
01 =
10 =
11 =
No division (counts every bit clock).
Divide by 2 (counts every 2 bit clocks).
Divide by 4 (counts every 4 bit clocks).
Divide by 8 (counts every 8 bit clocks).
HOLT INTEGRATED CIRCUITS
17
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
