HI-3110
DC ELECTRICAL CHARACTERISTICS (ctd.)
VLOGIC = 3.3V or 5V, VDD = 5V. Operating temperature range (unless otherwise noted).
LIMITS
TYP
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
MAX
Bus Lines (pins CANH, CANL)
CANH dominant output voltage
CANL dominant output voltage
VO(CANH)
VO(CANL)
See Fig 14. RL = 60 ꢀ
See Fig. 14. RL = 60 ꢀ
3
0.5
3.6
1.4
4.25
1.75
V
V
Matching of dominant output voltage,
VCC − VCANH − VCANL
VOM
− 100
0
0
150
mV
Dominant differential output voltage
Recessive differential output voltage
VDIFF(d)(o)
VDIFF(r)(o)
45 ꢀ < RL < 65 ꢀ, see Fig. 15
No Load
1.5
− 50
3
50
V
mV
Recessive output voltage
VCANH(r),
VCANL(r)
No Load, see Fig. 14
2
0.5VDD
3
V
Dominant differential input voltage (receiver)
Recessive differential input voltage (receiver)
Differential input hysteresis (receiver)
VDIFF(d)(i)
VDIFF(r)(i)
VDIFF(hys)
− 12 V < VCANH, VCANL < + 12 V
− 12 V < VCANH, VCANL < + 12 V
− 12 V < VCANH, VCANL < + 12 V
See Fig. 18
0.9
V
V
mV
0
70
0.5
Input leakage current
ICANH, ICANL
IO(sc)
VDD = 0 V (unpowered node)
− 200
− 200
+ 200
200
μA
Short circuit output current
pin CANH, VCANH = -58 V
pin CANL, VCANL = +58 V
See Fig. 16
mA
mA
Common mode input resistance
Deviation between common mode input resistance
RIN(CM)
RIN(CM)(m)
− 12 V < VCANH, VCANL < + 12 V
VCANH = VCANL
15
− 3
25
45
+ 3
kꢀ
%
Differential input resistance
SPLIT pin output voltage
RIN(DIFF)
Vsplit
− 12 V < VCANH, VCANL < + 12 V
25
50
75
kꢀ
V
Normal Mode
See Fig. 17
2.4
2.5
2.6
Common mode input capacitance1 (1Mbit/s data rate)
Differential input capacitance1 (1Mbit/s data rate)
CIN(CM)
CDIFF(CM)
20
10
pF
pF
HOLT INTEGRATED CIRCUITS
46
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
