HI-3110
Table 1. SPI Instruction Set (cont.)
SPI Instruction
Command Data Field
Hex
Bit Content
WRITE Commands
Write Transmit FIFO
0x12
N x (4 to 12 bytes) for Std frame or
N x (6 to 14 bytes) for Ext frame
(N = number of loaded messages, 1 - 8)
Write Control Register 0
Write Control Register 1
0x14
0x16
1 byte
1 byte
(see CTRL0 Register Definition)
(see CTRL1 Register Definition)
Write Bit Timing Register 0
Write Bit Timing Register 1
0x18
0x1A
1 byte
1 byte
(see BTR0 Register Definition)
(see BTR1 Register Definition)
Write Interrupt Enable Register
Write Status Flag Enable Register
0x1C
0x1E
1 byte
1 byte
(see INTE Register Definition)
(see STATFE Register Definition)
Write General Purpose Pins
Enable Register
0x22
1 byte
(see GPINE Register Definition)
Write REC Register (Test only)
Write TEC Register (Test only)
0x24
0x26
1 byte
1 byte
(see REC Register Definition)
(see TEC Register Definition)
Write Filter 0 ID
Write Filter 1 ID
Write Filter 2 ID
Write Filter 3 ID
Write Filter 4 ID
Write Filter 5 ID
Write Filter 6 ID
Write Filter 7 ID
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x72
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
(see Table 4a)
(see Table 4a)
(see Table 4a)
(see Table 4a)
(see Table 4a)
(see Table 4a)
(see Table 4a)
(see Table 4a)
Write Mask 0 ID
Write Mask 1 ID
Write Mask 2 ID
Write Mask 3 ID
Write Mask 4 ID
Write Mask 5 ID
Write Mask 6 ID
Write Mask 7 ID
0x74
0x76
0x78
0x7A
0x7C
0x7E
0x82
0x84
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
6 bytes
(see Table 4b)
(see Table 4b)
(see Table 4b)
(see Table 4b)
(see Table 4b)
(see Table 4b)
(see Table 4b)
(see Table 4b)
HOLT INTEGRATED CIRCUITS
34
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
