HI-3110
Table 3. Transmit History FIFO Data Format
Byte
Content
Bit Description (”x” = Don’t care)
x
x
1
2
3
Message Tag
Time Tag Upper Byte
Time Tag Lower Byte
specific to Extended IDs should be written as zeros for
Standard IDs. The filter mechanism works by comparing the
filter ID to the CAN message ID. If the corresponding bit in
the mask ID is logic one, then the CAN ID bit must match the
filter ID for acceptance to occur. If a mask ID bit is logic zero,
then acceptance will occur regardless of the value of the
CAN ID bit. In this case, the filter bits are don’t care.
HI-3110 Receive Buffers and Frame
Acceptance Filters
RECEIVE BUFFERS
The HI-3110 has an extremely flexible receive buffer and ID
filter scheme. Acceptance filters and masks may only be
programmed when the device is in Initialization Mode.
The basic concept is shown in figure 13. All valid received
messages (both standard or extended frames) are stored in
the temporary receive buffer before passing through the
filter bank. The host can read the temporary receive buffer
using SPI commands 0x42 or 0x44 (see table 1). The filter
bank must be enabled by setting the FILTON bit in Control
Register, CTRL1. The default after reset is FILTON = 0,
which disables the filter bank and stores every valid
message received in the FIFO. With filtering enabled, it is
possible to filter up to eight extended identifiers plus the first
two associated data bytes. Any filtered messages will be
passed to the receive FIFO. Up to eight messages can be
stored in the receive FIFO. All valid received messages
have a 16-bit time tag appended following transmission of
the ACK bit. The user can decide to retrieve the time tag or
not via dedicated SPI instructions (seeTable 1).
Following reset, all eight filter and mask registers should be
loaded before enabling the FILTON bit. Note that following
reset, filter and mask bits are not reset, therefore the
FILTON bit may be set to enable filtering using the pre-reset
mask and filter values.
READING THE RECEIVE BUFFERS VIASPI
Table 1 summarizes the SPI instructions for reading the
receive buffers. The host has a choice of retrieving a
message with a 16-bit time tag or not. The receive data
format is shown in Table 5. The first data byte identifies
whether the frame was standard or extended format and the
FILHIT2:0 bits identify which filter passed the message;
<000> to <111>. If more than one filter passed the message,
the lowest value will be given priority and be identified by the
FILHIT2:0 bits. As can be seen in Table 5, bits specific to
extended frames will be read as zeros for standard frames.
If the received data does not contain an 8 byte payload (8
data bytes), the HI-3110 will pad the remaining data bytes
with zeros. The host should keep CS low for the duration of
the SPI sequence.
FILTERAND MASK ID FORMAT
The HI-3110 allows filtering of up to 8 unique extended
frames with the first two data bytes. Filtering is enabled by
setting the FILTON bit in Control Register 1, CTRL1. It the
FILTON bit is not set, then filtering is globally disabled and all
CAN IDs are accepted.
There is a specific SPI instruction for loading and reading
each filter and mask. The format is the same for both
standard and extended IDs and is shown in Table 4. Bits
HOLT INTEGRATED CIRCUITS
39
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
