HI-3110
REGISTERS
This section describes the HI-3110 registers. All register bits are active high. Unless otherwise indicated, all registers are reset
in software to the logic zero condition after Master Reset. For all registers, bit 7 is the most significant:
REGISTER
R/W
DESCRIPTION
SPI WRITE
OP-CODE
SPI READ
OP-CODE
CTRL0
CTRL1
BTR0
BTR1
TEC
REC
MESSTAT
ERR
INTF
R/W
R/W
R/W
R/W
R/W
R/W
R
Configuration Register 0
Configuration Register 1
BitTiming Register 0
0x14
0x16
0x18
0x1A
0x26
0x24
N/A
N/A
N/A
0x1C
N/A
0xD2
0xD4
0xD6
0xD8
0xEC
0xEA
0xDA
0xDC
0xDE
OxE4
0xE2
0xE6
0xE8
0xFA*
0xFA*
BitTiming Register 1
Transmit Error Counter Register
Receive Error Counter Register
Message Status Register
Error Register
Interrupt Flag Register
Interrupt Enable Register
Status Flag Register
Status Flag Enable Register
General Purpose Pins Enable Register
Free-RunningTimer Upper Byte Register
Free-RunningTimer Lower Byte Register
R
R
INTE
R/W
R
R/W
R/W
R
STATF
STATFE
GPINE
TIMERUB
TIMERLB
0x1E
0x22
N/A
R
N/A
Note: Free-running counter registers, TIMERUB:TIMERLB are read with a single SPI Op-code (0xFA) as a 16-
bit value in two SPI data bytes.
Power-On-Reset
Following power-on, the HI-5110 will automatically perform a Master Reset and return all registers to the default state.
Following reset, the device will default to Initialization Mode to allow programming of Control and Bit Timing Registers (see
following sections).
HOLT INTEGRATED CIRCUITS
16
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
