HI-3110
BIT TIMING REGISTER 0: BTR0
SJW0BRP5
BRP1BRP0
(Write, SPI Op-code 0x18)
(Read, SPI Op-code 0xD6)
7
6
5
4
3
2
1
0
LSB
MSB
BTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP). This register can be read
anytime and written only in init mode (MODE<2:0> bits set to <1xx> in the CTRL0 register).
Bit Name
R/W Default Description
7-6 SJW1:0
R/W
0
Re-synchronization Jump Width bits <1:0>.
These bits are used to compensate for phase shifts between different clock oscillators on the
bus. They define the maximum number of time quanta (Tq) a bit can be shortened or
lengthened to allow a node achieve re-synchronization to the edge of an incoming signal.
Note that one time quantum (Tq) is the single unit of time within a bit time (see BitTiming
section).
SJW bits <1:0>
00: SJW = 1Tq
01: SJW = 2Tq
10: SJW = 3Tq
11: SJW = 4Tq
Note:ARINC 825 states that the Re-synchronization Jump Width shall be 1Tq
5-0 BRP5:0
R/W
0
Baud Rate Prescaler bits <5:0>.
The baud rate prescaler relates the system oscillator frequency, fOSC, to the CAN bit time as
described in the bit timing section.
BRPbits <5:0>
000000: BRP= 1
000001: BRP= 2
000010: BRP= 3
000011: BRP= 4
.
etc.
.
111111: BRP = 64
HOLT INTEGRATED CIRCUITS
19
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
