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HI-3110PCIF 参数 Datasheet PDF下载

HI-3110PCIF图片预览
型号: HI-3110PCIF
PDF下载: 下载PDF文件 查看货源
内容描述: 航空电子与CAN收发器集成控制器 [Avionics CAN Controller with Integrated Transceiver]
分类和应用: 电子控制器航空
文件页数/大小: 53 页 / 178 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3110  
BIT WISEARBITRATION  
Bitwise arbitration works by comparing each node’s  
transmitted data bit by bit. All nodes are synchronized by  
adjusting individual bit times as a function of bit time quanta  
(see section on bit timing). Synchronization takes place on  
recessive to dominant edges. AHard Synchronization at the  
start of each frame and subsequent re-synchronizations  
during a message frame ensures corresponding bits match  
in time during a given transmission cycle. When a node  
transmits a recessive bit on the bus, but detects a dominant  
bit on it’s receiver, it realizes arbitration is lost and it  
immediately ceases transmission and becomes a receiver.  
It will then wait for the next bus idle state and attempt to re-  
transmit. Eventually, lower priority messages will gain  
access to the bus. Figure 7 shows an example of how this  
works for a frame with a standard identifier.  
The CAN standard resolves data contention on the bus  
a scheme called Carrier Sense Multiple  
using  
Access/Collision Detection-Carrier Resolution (CSMA/CD-  
CR).  
Carrier Sense: Each node waits for a period without bus  
activity (bus idle state) before attempting transmission.  
Multiple Access: Every node on the bus has equal access  
to the bus for transmitting.  
Collision Detection: Collisions occur if two nodes attempt  
to transmit at the same time.  
Collision Resolution: Collisions are resolved by bitwise  
arbitration.  
Highest priority messages (lowest binary  
identifiers) are sent first without delay and lower-priority  
messages are automatically re-transmitted later.Adominant  
bit (logic 0) has priority over a recessive bit (logic 1).  
Standard ID Arbitration Field  
TXCAN: Node 1  
TXCAN: Node 2  
TXCAN: Node 3  
1
0
1
0
1
0
CAN Bus differential  
signal (not to scale)  
Node 2 loses arbitration  
Node 3 loses arbitration  
Figure 7. Bitwise Arbitration.  
HOLT INTEGRATED CIRCUITS  
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