HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
HI-318X PACKAGE THERMAL CHARACTERISTICS
MAXIMUM ARINC LOAD
PACKAGE STYLE
1
3, 6, 7
HEAT SINK
Unsoldered
Soldered
Unsoldered
Soldered
N/A
ØJA
(°C/W)
82
65
51
28
70
SUPPLY CURRENT
20 mA
20 mA
20 mA
20 mA
25 mA
2
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
57°C
51°C
45°C
36°C
56°C
117°C
111°C
105°C
96°C
110°C
157°C
151°C
145°C
136°C
150°C
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
28-pin Plastic
A
OUT
and B
OUT
Shorted to Ground
PACKAGE STYLE
1
3, 4, 5, 6, 7
HEAT SINK
Unsoldered
Soldered
Unsoldered
Soldered
N/A
ØJA
(°C/W)
82
65
51
28
70
SUPPLY CURRENT
36 mA
36 mA
40 mA
40 mA
63 mA
2
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
57°C
78°C
64°C
53°C
100°C
147°C
138°C
124°C
113°C
150°C
187°C
178°C
164°C
153°C
182°C
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
28-pin Plastic
Notes:
1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062").
2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
4. Similar results would be obtained with A
OUT
shorted to B
OUT
.
5. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
6. Data will vary depending on air flow and the method of heat sinking employed.
7. Current values listed are for each of the +V and -V supplies.
HEAT SINK - ESOIC PACKAGES
Both the 14-pin and 16-pin thermally enhanced SOIC
packages are used for HI-318X products. These ESOIC
packages include a metal heat sink located on the bottom
surface of the device. This heat sink should be soldered
down to the printed circuit board for optimum thermal
dissipation. The heat sink is electrically isolated from the
chip and can be soldered to any ground or power plane.
However, since the chip’s substrate is at +V, connecting
the heat sink to this power plane is recommended to avoid
coupling noise into the circuit.
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
