HI-3000, HI-3001, HI-3002
FUNCTIONAL DESCRIPTION
OPERATING MODES
The HI-3000 provides two modes of operation which are
selectable via the STB pin. Table 1 summarizes the modes.
Table 1 - Operating Modes
due to an unpowered node with high leakage from the bus
lines to ground), the split circuit will force the recessive
voltage to VDD/2.
INTERNAL PROTECTION FEATURES
Short-circuit protection
Short-circuit protection is provided on the CANH, CANL and
SPLIT pins. These pins are protected from ESD to over 6KV
(HBM) and from shorts between -58V and +58V continuous,
as specified in ISO 11898-5. The short circuit current is limited
to less than 200mA typical.
TXD permanent dominant time-out
Normal Mode
Normal mode is selected by setting the STB pin to a LOW
logic level (GND). In this mode, the transceiver transmits and
receives data in the usual way from the CANH and CANL bus
lines. The differential receiver converts the analog bus data
to digital data which is output on the RXD pin (Note: the RXD
output on HI-3001 is compatible with 3.3V controllers if the
VIO pin is connected to a 3.3V supply).
Standby Mode
Standby Mode is selected by setting the STB pin to a HIGH
logic level. In this mode, the transmitter is switched off and a
low power differential receiver monitors the bus lines for
activity. A dominant signal of more than 3
m
s will be reflected
on the RXD pin as a logic LOW, where it may be detected by
the host as a wake-up request. The device will not leave
standby mode until the host forces the STB pin to a logic low.
A timer circuit prevents the bus lines being driven into a
permanent dominant state, which would result in a situation
blocking all bus traffic. This could happen in the case of the
TXD pin becoming permanently low due to a hardware or
application failure. The timer is triggered by a negative edge
on the TXD pin (start of dominant state). If the TXD pin is not
set high (recessive state) after a typical time of 2ms, the
transmitter outputs will be disabled, driving the bus lines into
the recessive state. The timer is reset by a positive edge on
the TXD pin. Note that the minimum TXD dominant time-out
time, tdom = 300μs, defines the minimum possible bit rate of
40kbit/s (the CAN protocol specifies a maximum of 11
successive dominant bits − 5 successive dominant bits
immediately followed by an error frame).
Fail-safe features
Pin TXD has a pull up in order to force a recessive level if pin
TXD is left open.
Pins TXD and STB will become floating if power is lost. This
will prevent reverse currents via these pins.
MODE
Normal
Standby
STB pin
LOW
HIGH
SPLIT Circuit
The SPLIT pin provides a stable VDD/2 DC voltage. This
pin can be used to stabilize the recessive common mode
voltage by connecting the SPLIT pin to the center tap of the
split termination (see figure 7). In the case of a recessive
bus voltage dropping below the ideal value of VDD/2 (e.g.
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
