HI-1573, HI-1574
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
TRANSMITTER
(Measured at Point “AD” in Figure 2 unless otherwise specified)
35 ohm load
(Measured at Point “AD“ in Figure 2)
Output Voltage
Direct coupled
VOUT
.6.0
9.0
Vp-p
70 ohm load
(Measured at Point “AT“ in Figure 3)
Transformer coupled
VOUT
VON
.18.0
27.0
10.0
90
Vp-p
mVp-p
mV
Output Noise
Differential, inhibited
35 ohm load
(Measured at Point “AD“ in Figure 2)
Output Dynamic Offset Voltage
Direct coupled
VDYN
-90
70 ohm load
(Measured at Point “AT“ in Figure 3)
Transformer coupled
VDYN
-250
10
250
15
mV
Output resistance
ROUT
COUT
Differential, not transmitting
1 MHz sine wave
Kohm
pF
Output Capacitance
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RECEIVER
(Measured at Point “AT” in Figure 3)
Receiver Delay
tDR
tRG
From input zero crossing to RXA/B or RXA/B
500
Note 3
430
ns
ns
Receiver gap time
Spacing between RXA/B and RXA/B pulses
60
Note 1
Note 2
Receiver Enable Delay
From RXENA/B rising or falling edge to
RXA/B or RXA/B
tREN
40
ns
TRANSMITTER (Measured at Point “AD” in Figure 2)
Driver Delay
Rise time
tDT
tr
TXA/B, TXA/B to BUSA/B, BUSA/B
35 ohm load
150
300
300
100
150
ns
ns
ns
ns
ns
100
100
Fall Time
tf
35 ohm load
Inhibit Delay
tDI-H
tDI-L
Inhibited output
Active output
Note 1. Measured using a 1 MHz sinusoid, 20 V peak to peak, line to line at point “AT” (Guaranteed but not tested).
Note 2. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT” (100% tested).
Note 3. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT”. Measured from input zero crossing point.
TRANSMITTER
1:2.5
55 W
BUSA/B
TXA/B
35 W
Point “AD“
TXA/B
BUSA/B
55 W
Isolation
Transformer
TXINHA/B
RECEIVER
2.5:1
55 W
RXA/B
RXA/B
Point “AD“
35 W
55 W
Isolation
Transformer
RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS
5