HI-1567, HI-1568
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
15
SYMBOL
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
RXB
RXB
TXINHB
TXB
TXB
RXA
RXA
TXINHA
TXA
TXA
FUNCTION
power supply
analog output
analog output
digital input
power supply
power supply
analog output
analog output
digital input
power supply
digital output
digital output
digital input
digital input
digital input
digital output
digital output
digital input
digital input
digital input
+5 volt power for channel A
DESCRIPTION
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568)
Ground for channel A
+5 volt power for channel B
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568)
Ground for channel B
Receiver B output, inverted
Receiver B outpot, non-invertedl
Transmit inhibit, channel B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
Receiver A output, non-inverted
Transmit inhibit, channel A. If high BUSA, BUSA disabled
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1567 family of data bus transceivers contain differ-
ential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
TRANSMITTER
RECEIVER
Data input to the transmitter section of these devices is
from the complimentary CMOS /TTL inputs TXA/B and
TXA/B. This produces a nominal 30V peak to peak signal
across a 140 ohm load. The transmitter is connected to the
bus via a 1:2.5 transformer whose secondary is connected
to two 52 ohm isolation resisters which feed the terminated
70 ohm bus. This will produce a nominal voltage on the bus
of 7.5 volts peak to peak.
The receiver is transformer coupled to the bus by a 1:1
transformer. Its differential input stage drives a filter and
threshold comparator. CMOS/TTL data is outputted at the
RXA/B and RXA/B pins.
The receiver outputs can both be forced to a logic "0"
(HI-1567) or logic “1” (HI-1568) by setting RXENA or
RXENB low.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are ei-
ther at a logic “1” or logic “0” simultaneously. A logic “1:” ap-
plied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
TXA/B
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
