HT48R063B/064B/065B/066B
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
Power-on
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(Idle/Sleep)
Register
(Normal Operation)
PCL
MP0
MP1
MP0
MP1
ACC
TBLP
0 0 0 0 0 0 0 0
1 x x x x x x x
1 x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
- - x x x x x x
- x x x x x x x
- - - - - 1 1 1
- - 0 0 x x x x
- 0 0 0 0 0 0 0
- - - 0 - - - 0
x x x x x x x x
0 0 0 0 1 0 0 0
x x x x x x x x
0 0 0 0 1 - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- - 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
- - - - 0 0 0 0
- 0 - - 0 0 0 0
1 0 0 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 u u u u u u u
1 u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u u u u u
- u u u u u u u
- - - - - 1 1 1
- - u u u u u u
- 0 0 0 0 0 0 0
- - - 0 - - - 0
x x x x x x x x
0 0 0 0 1 0 0 0
x x x x x x x x
0 0 0 0 1 - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
- - - - 0 0 0 0
- 0 - - 0 0 0 0
1 0 0 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 u u u u u u u
1 u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u u u u u
- u u u u u u u
- - - - - 1 1 1
- - 1 u u u u u
- 0 0 0 0 0 0 0
- - - 0 - - - 0
x x x x x x x x
0 0 0 0 1 0 0 0
x x x x x x x x
0 0 0 0 1 - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
- - - - 0 0 0 0
- - - - 0 0 0 0
- 0 - - 0 0 0 0
1 0 0 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 u u u u u u u
1 u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u u u u u
- u u u u u u u
- - - - - u u u
- - 1 1 u u u u
- u u u u u u u
- - - u - - - u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
- - u u u u u u
- - u u u u u u
- - u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - u u u u
- - - - u u u u
- - - - u u u u
- - - - u u u u
- u - - u u u u
u u u u u u u u
u u u u u u u u
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
TBLH
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
WDTS
STATUS
INTC0
INTC1
TMR0
TMR0C
TMR1
TMR1C
PA
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
PAC
PAWK
PAPU
PB
PBC
PBPU
PC
PCC
PCPU
PD
PDC
PDPU
·
·
·
CTRL0
·
·
·
CTRL1
·
·
·
·
SCOMC
Note:
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
32
April 7, 2011