HT48R50A-1/HT48C50-1
The functional unit chip reset status are shown below.
Program Counter
Interrupt
000H
Disable
Clear
Prescaler
WDT
Clear. After master reset, WDT begins counting
Timer/Event Counter
Input/Output Ports
Stack Pointer
Off
Input mode
Points to the top of the stack
The states of the registers is summarized in the table.
Reset
(Power-on)
WDT Time-out RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
TMR0
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
TMR0C
TMR1H
TMR1L
TMR1C
Program
Counter
000H
000H
000H
000H
000H
MP0
MP1
ACC
TBLP
TBLH
STATUS
INTC
WDTS
PA
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--1u uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
PAC
PB
PBC
PC
PCC
PD
PDC
PG
PGC
---- -111
---- -111
---- -111
---- -111
---- -uuu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 2.00
13
March 8, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
