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HT48CA0-2 参数 Datasheet PDF下载

HT48CA0-2图片预览
型号: HT48CA0-2
PDF下载: 下载PDF文件 查看货源
内容描述: 遥控型8位MCU [Remote Type 8-Bit MCU]
分类和应用: 微控制器和处理器外围集成电路遥控LTE
文件页数/大小: 32 页 / 235 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48RA0-2/HT48CA0-2  
Instruction  
Cycle  
Flag  
Mnemonic  
Branch  
Description  
Affected  
JMP addr  
SZ [m]  
Jump unconditionally  
2
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
Skip if data memory is zero  
1(2)  
1(2)  
1(2)  
1(2)  
1(3)  
1(3)  
1(2)  
1(2)  
2
SZA [m]  
SZ [m].i  
SNZ [m].i  
SIZ [m]  
Skip if data memory is zero with data movement to ACC  
Skip if bit i of data memory is zero  
Skip if bit i of data memory is not zero  
Skip if increment data memory is zero  
Skip if decrement data memory is zero  
Skip if increment data memory is zero with result in ACC  
Skip if decrement data memory is zero with result in ACC  
Subroutine call  
SDZ [m]  
SIZA [m]  
SDZA [m]  
CALL addr  
RET  
Return from subroutine  
2
RET A,x  
Return from subroutine and load immediate data to ACC  
2
Table Read  
TABRDC [m] Read ROM code (current page) to data memory and TBLH  
TABRDL [m] Read ROM code (last page) to data memory and TBLH  
2(1)  
2(1)  
None  
None  
Miscellaneous  
NOP  
No operation  
1
1(1)  
1(1)  
1
None  
None  
CLR [m]  
Clear data memory  
SET [m]  
Set data memory  
None  
CLR WDT  
CLR WDT1  
CLR WDT2  
SWAP [m]  
SWAPA [m]  
HALT  
Clear Watchdog Timer  
TO,PDF  
TO(4),PDF(4)  
TO(4),PDF(4)  
None  
Pre-clear Watchdog Timer  
Pre-clear Watchdog Timer  
Swap nibbles of data memory  
Swap nibbles of data memory with result in ACC  
Enter power down mode  
1
1
1(1)  
1
None  
1
TO,PDF  
Note: x: Immediate data  
m: Data memory address  
A: Accumulator  
i: 0~7 number of bits  
addr: Program memory address  
Ö: Flag is affected  
-: Flag is not affected  
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle  
(four system clocks).  
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more  
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.  
(1) and (2)  
(3)  
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the  
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.  
Otherwise the TO and PDF flags remain unchanged.  
Rev. 1.50  
14  
July 23, 2004