HT48R05A-1/HT48C05/HT48R06A-1/HT48C06/HT48R08A-1
been backed up. All table related instructions require
20H to 7FH (HT48R08A-1), is used for data and control
information under instruction commands.
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
Stack Register - STACK
This is a special part of the memory which is used to save
the contents of the Program Counter only. The stack is or-
ganized into 2 levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the con-
tents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program coun-
ter is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result ²1². Any writing operation to MP will only transfer
the lower 7-bit data to MP.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 2 return ad-
dresses are stored).
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
Data Memory - RAM
The data memory is designed with 49´8 bits
(HT48R05A-1/HT48C05), 81´8 bits (HT48R06A-1/
HT48C06) or 113´8 bits (HT48R08A-1). The data
memory is divided into two functional groups: special
function registers and general purpose data memory
32´8 (HT48R05A-1/HT48C05), 64´8 (HT48R06A-1/
HT48C06) or 96´8 (HT48R08A-1). Most are
read/write, but some are read only.
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
The special function registers include the indirect ad-
dressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer register (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H). The remain-
ing space before the 60H (HT48R05A-1/HT48C05),
40H (HT48R06A-1/HT48C06) or 20H (HT48R08A-1) is
reserved for future expanded usage and reading these
locations will get ²00H². The general purpose data
memory, addressed from 60H to 7FH (HT48R05A-1/
HT48C05), 40H to 7FH (HT48R06A-1/HT48C06) or
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition opera-
tions related to the status register may give different re-
sults from those intended. The TO flag can be affected
only by system power-up, a WDT time-out or executing
the ²CLR WDT² or ²HALT² instruction. The PDF flag
can be affected only by executing the ²HALT² or ²CLR
WDT² instruction or a system power-up.
Rev. 1.50
7
August 22, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
